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Projects / Programmes source: ARIS

Computer structures and systems

Periods
Research activity

Code Science Field Subfield
2.07.00  Engineering sciences and technologies  Computer science and informatics   

Code Science Field
T120  Technological sciences  Systems engineering, computer technology 
T170  Technological sciences  Electronics 
P170  Natural sciences and mathematics  Computer science, numerical analysis, systems, control 
Evaluation (rules)
source: COBISS
Researchers (8)
no. Code Name and surname Research area Role Period No. of publicationsNo. of publications
1.  11983  PhD Anton Biasizzo  Computer science and informatics  Researcher  2001 - 2003  149 
2.  17040  PhD Uroš Kač  Computer science and informatics  Researcher  2001 - 2003  35 
3.  22314  PhD Peter Korošec  Computer science and informatics  Researcher  2002 - 2003  238 
4.  10824  PhD Barbara Koroušić Seljak  Computer science and informatics  Researcher  2001 - 2003  341 
5.  05601  PhD Franc Novak  Computer science and informatics  Head  2001 - 2003  316 
6.  18291  PhD Gregor Papa  Computer science and informatics  Researcher  2001 - 2003  352 
7.  09862  PhD Jurij Šilc  Computer science and informatics  Researcher  2001 - 2003  359 
8.  14081  PhD Alenka Žužek  Computer science and informatics  Researcher  2001 - 2003  49 
Organisations (1)
no. Code Research organisation City Registration number No. of publicationsNo. of publications
1.  0106  Jožef Stefan Institute  Ljubljana  5051606000  91,044 
Abstract
Research activities are concerned primarily with the fields of design automation of integrated circuits and computer systems. In this broad area, we are concentrating particularly on high-level architectural synthesis, verification and test. We aim to develop hardware-software codesign methodologies and tools for systematic and concurrent development of the hardware and software components of a complex reactive and embedded system, providing interaction and exploration of trade-offs along the design process: system-level specification and modeling, automatic synthesis, and validation. Expected research and application contributions include investigation of different partitioning and scheduling schemes using high performance evolutionary heuristics (e.g. simulated annealing, genetic optimization, neurocomputing), and development of a synthesis compiler, i.e. a computer aided system that automatically translates the system-level specification into the hardware and software description languages from which physical elements can be built. We are also developing a real-time executive, i.e. a prototyping tool that provides software support on the target architecture and schedules the synthesized model components. Practical applications in machine vision are foreseen. Increasing complexity of integrated circuits necessiates design-for-testability in all levels of design including high-level synthesis. In this area we investigate methods for generation of on-line concurrent built-in test structures based on idle system units. In our approach the objective is not only to minimize the cost of the inserted test logic by exploiting idle operators but also to ensure a high test quality in terms of error latency and fault coverage. We also address problems of test and diagnosis at lower design levels. Experimental case studies employing boundary-scan and mixed-signal test bus solutions are performed. Problems in the area of VLSI design require an efficient underlying data structure. We investigate the full potential of AND/OR graphs in VLSI CAD for logic design and testing. For this purpose, an experimental environment for the generation of AND/OR graphs has been developed. Correspondence between the generated AND/OR graphs and minimal binary decision diagrams is studied.
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