Low-Power Reconfigurable Fault-Tolerant Platforms

Embedded Systems (ESs) represent the major market of microprocessors. Recently there has been a definite tendency to utilize ESs in real time applications in which high performance and re-configurability, fault tolerance and reduced energy consumption are desirable. Within the framework of this project efficient solving of the three problems will be in focus of interest. Since field programmable gate arrays (FPGAs) were introduced there have radically changed the way digital logic is designed and deployed. FPGAs have made possible to use in numerous embedded applications. The first main goal of this project is to make designers comfortable with these issues, and able to exploit a vast opportunity that offers the reconfigurable logic. Modern ES architectures present new challenges to fault tolerant (FT) design engineers. Much previous work in FT hardware design focused on gate-level approaches, but now more work is needed at much higher level of abstraction, making complete design validation more difficult. The second goal this project is to prepare design engineers how to set trade-off point between fault tolerance, performance, and low power consumption. Today, the power consumption of ESs is considered as one of the most important problems for portable devices. This is due to the limited cell battery lifetime. The third goal of this project is to navigate researchers towards design of efficient power management and energy harvesting circuitries implemented in ES devices.